Dynamic random access memories (DRAMs) may be generally constructed as shown in U.S. Pat. No. 4,081,701 (a 16 kbit (DRAM) issued to White, McAdams and Redwine and assigned to Texas Instruments, Inc., and in U S. Pat. No. 4,239,993 (a 64 kbit DRAM) issued to McAlexander, White and Rao and assigned to Texas Instruments, Inc.
Complementary-metal-oxide (CMOS) semiconductor technology has been incorporated into the design of peripheral circuits for DRAMs. For example, U.S. Pat. No. 4,555,777 issued to Poteet and assigned to Texas Instruments, Inc. discloses DRAMs containing CMOS sense amplifiers. Among other advantages, CMOS technology aids in reducing the power consumed by the DRAM device.
An important consideration in the overall design of a memory system is the standby current drawn by a DRAM while it is inactive, since to a large degree this parameter determines the power consumed by the memory system. A significant portion of the standby current drawn by the DRAM comes from its first inverter connected to the Row Address Strobe (RAS) input. This inverter is required to be active (i.e., powered up) at all times in order to respond to a RAS signal that initiates a cycle and when the system wants to refresh the dynamically stored data. However, with a voltage supply typically of 5 v and transistor-transistor-logic (TTL) input signal levels (where typically 0.8 v is a "low" signal and 2.4 v is a "high" signal), CMOS input buffers consume current while in standby because the TTL "high" level input is not sufficient to turn the top p-channel transistor of its first CMOS inverter completely off. This allows a DRAM to consume power while in standby through a DC current path existing through the source/drain paths of the p-channel and n-channel transistors of the CMOS inverter of the input buffer.
Another important consideration in system design is the current consumed by a DRAM during initial power up before stable input voltage levels can be guaranteed. This problem occurs when the RAS input is at a level between the specified logic "low" and the specified logic "high". Between these levels, the input buffer may oscillate due to the RAS input fluctuating above and below the trip point of the first inverter of the input buffer. The trip point of the inverter is the level of voltage between the specified logic "low" and the specified logic "high" at which its p-channel transistor and its n-channel transistor switch. As RAS varies above and below this voltage level, the inverter accordingly varies as its transistors repeatedly switch on and off. This can cause the DRAM to go into oscillation that causes a large current drain on the external power supply. When this current drain is multiplied by the typically large number of memory chips located in a memory system, oscillation can load the system power supply and prevent it from coming up to the required voltage level in time.
It is an object of this invention to provide an input buffer that reduces the standby current drawn by a DRAM.
It is a further object of this invention to provide an input buffer that reduces DRAM oscillation.
Other objects and benefits of this invention will be apparent to those skilled in the art, based upon the description to follow herein.